1. Field of the Invention
The present invention relates generally to a semiconductor memory device, and more particularly, to a charge trapping memory device with two separated non-conductive charge trapping inserts and a method for making such a device.
2. Description of the Related Art
As is well known in the art, a nitride read only memory (NROM) device uses an oxide-nitride-oxide (ONO) structure as the gate insulator as well as the charge trapping layer. A NROM device is programmed by injecting electrons into the nitride layer of the ONO structure via the channel hot electron (CHE) injection method. The trapped electrons in the nitride layer of the ONO structure can be erased by injecting holes into the place where the electrons are stored via the band-to-band hot (BTBH) hole injection method.
Although a NROM device is widely used in the semiconductor industry, it has the following drawbacks. First of all, a NROM device has a hard-to-erase problem after cycling. During the erasing process of an NORM device via the BTBH hole injection method, it is difficult to inject the holes to exactly where the electrons are trapped, and it is hard to match exactly the number of the trapped electrons with the number of injected holes, which leads to the phenomenon of the hard-to-erase problem. Next, an NROM device has wide threshold voltage VT distribution. In fabricating an NROM device, the plasma charging or UV-charging process can cause the initial VT to shift and broaden. If some of the injected electrons are shifted towards the center of the nitride layer of the ONO structure that is far away from the place where the electrons are injected, the initial wide VT distribution is further out of control. The wide VT distribution cannot be reset back to a lower state. Furthermore, an NROM device could have severe second bit effect. Because an NROM device is capable of 2-bit operation by storing two charges towards the ends of the nitride layer of the ONO structure, as the charges at both ends of the nitride layer of the ONO structure gets larger, the charges of both bits will interact with each other during a reverse read operation, which leads to the undesirable second bit effect. Finally, an NROM device has a hard-to-shrink problem due to the fact that its doping profile mainly controls the electron profile. Thus, the local charge profile will overlap with the other local charge profile, which makes an NROM device difficult to shrink.
Another prior art floating gate memory device utilizes two separated polysilicon inserts in the gate insulator next to the junctions. This floating gate memory device will have reliability problems such as stress-induced leakage current (SILC) and erratic bits.
In view of the foregoing, there is a need for a new charge trapping memory device and its fabrication method that will overcome the above-mentioned drawbacks of the NROM device and a floating gate memory device.